Spi clock interruption

Build your own
1

Hi,

I’m using a custom WP7702 board and have strange behavior on the SPI bus. When sending 16 bytes in one write command, I see short bursts of 8-bits and then the clock pauses for 25us before sending the next 8 bits. I am expecting a continuous clock while sending all 16 bytes.

Firmware 14.1, legato 19.11.5

The code i used:

COMPONENT_INIT
{
    LE_INFO("===========> SPI application has started");

    le_result_t res;

    le_spi_DeviceHandleRef_t spiHandle;
    res = le_spi_Open("spidev1.0", &spiHandle);
    LE_FATAL_IF(res != LE_OK, "spi_Open failed with result=%d", res);

    LE_INFO("Configuring SPI");
    le_spi_Configure(spiHandle, 0, 8, 960000, 0);

    LE_INFO("Performing a SPI write of 16 bytes");
    {
        const uint8_t writeData[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
        LE_ASSERT_OK(le_spi_WriteHD(spiHandle, writeData, NUM_ARRAY_MEMBERS(writeData)));
    }
    LE_INFO("SPI write completed successfully");

    le_spi_Close(spiHandle);
}

This is the result from the scope:

SPI_probleem
SPI_probleem1280×824 17 KB

C3 (orange) is the SPI clock signal
C4 (purple) is the SPI data signal

Does anyone know what causes this? The speed is cut by a factor 4 and I have a slave that does not like the interruption.

Best regards,
Frans.

2

you can check on yocto source:
./kernel/drivers/spi/spi.c

I saw it has added some delay, not sure if this is related, you can try to modify it.

static int spi_transfer_one_message(struct spi_master *master,
				    struct spi_message *msg)
{
	struct spi_transfer *xfer;
	bool keep_cs = false;
	int ret = 0;
	int ms = 1;

	spi_set_cs(msg->spi, true);

	list_for_each_entry(xfer, &msg->transfers, transfer_list) {
		trace_spi_transfer_start(msg, xfer);

		if (xfer->tx_buf || xfer->rx_buf) {
			reinit_completion(&master->xfer_completion);

			ret = master->transfer_one(master, msg->spi, xfer);
			if (ret < 0) {
				dev_err(&msg->spi->dev,
					"SPI transfer failed: %d\n", ret);
				goto out;
			}

			if (ret > 0) {
				ret = 0;
				ms = xfer->len * 8 * 1000 / xfer->speed_hz;
				ms += ms + 100; /* some tolerance */

				ms = wait_for_completion_timeout(&master->xfer_completion,
								 msecs_to_jiffies(ms));
			}

			if (ms == 0) {
				dev_err(&msg->spi->dev,
					"SPI transfer timed out\n");
				msg->status = -ETIMEDOUT;
			}
		} else {
			if (xfer->len)
				dev_err(&msg->spi->dev,
					"Bufferless transfer has length %u\n",
					xfer->len);
		}

		trace_spi_transfer_stop(msg, xfer);

		if (msg->status != -EINPROGRESS)
			goto out;

		if (xfer->delay_usecs)
			udelay(xfer->delay_usecs);

		if (xfer->cs_change) {
			if (list_is_last(&xfer->transfer_list,
					 &msg->transfers)) {
				keep_cs = true;
			} else {
				spi_set_cs(msg->spi, false);
				udelay(10);
				spi_set_cs(msg->spi, true);
			}
		}

		msg->actual_length += xfer->len;
	}

out:
	if (ret != 0 || !keep_cs)
		spi_set_cs(msg->spi, false);

	if (msg->status == -EINPROGRESS)
		msg->status = ret;

	spi_finalize_current_message(master);

	return ret;
}
3

Thank you for your reply! I’m not very familiar with compiling kernel drivers but I will try to change the code and see if this helps.

Best regards,
Frans.